1. Field of the Invention
This invention relates to a bus bridge circuit, bus connection system, and buffer control method for a bus bridge circuit to connect two PCI buses or similar and performs data transfer between two buses, and in particular, relates to a bus bridge circuit, bus connection system, and buffer control method for a bus bridge circuit to control a buffer which stores data for transfer between two buses.
2. Description of the Related Art
Various functional devices are connected by buses in computer systems to realize various functions. With the spread of personal computers in recent years, controller or similar are constructed by connecting functional devices developed for personal computers by a Peripheral Component Interconnect (PCI) bus.
On the other hand, when devices with different functions are connected by a bus, it is effective to provide bridge circuits in the bus between devices. FIG. 6 is a drawing of the conventional configuration of a bridge circuit (PCI bridge circuit) connected to PCI buses; FIG. 7 is a drawing of the timing chart of transfer operation of the bridge circuit.
The PCI bridge circuit 104 is connected to two PCI buses 200, 300, and performs data transfer between a PCI device 100 connected to the PCI bus 200, and a PCI device 102 connected to the PCI bus 300. The PCI bridge circuit. 104 comprises a FIFO (fast-in fast-out) buffer 114 which stores transfer data; a target control circuit 110 which performs control as the target, as seen by the PCI device; and a master control circuit 112 which performs control as the master, as seen by the PCI device.
In the case (called writing) in which data is transferred from the PCI device 100 to the PCI device 102, a write request is issued to the PCI bridge circuit 104 from the PCI device 100, and then a write request is issued to the PCI device 102 from the PCI bridge circuit 104. The PCI bridge circuit 104 temporarily writes the data received from the PCI device 100 via the primary-side PCI bus 200 to the FIFO buffer 114, and then transfers the data to the PCI device 102 via the secondary-side PCI bus 300.
This is explained in detail using FIG. 7. First, the PCI device 100 issues a write request to the PCI bridge circuit 104, and then *IRDY (Initiator Ready) 2 is set to low (the ready state). By this means, the PCI bridge circuit 104 enters the state to receive data; then *TRDY (Target Ready) 2 input to the PCI device 100 is set low (the ready state).
The PCI device 100 confirms that both the ready signals *IRDY2 and *TRDY2 are low, and then outputs the transfer data to the primary-side PCI bus 200. At the PCI bridge circuit 104, this transfer data is written in sequence to the FIFO buffer 114.
On the other hand, the PCI bridge circuit 104 performs internal processing according to the PCI bus protocol, acquires bus ownership, and establishes a data transfer state with the PCI device 102, then the PCI bridge circuit 104 issues a write request to the PCI device 102, and sets *IRDY (Initiator Ready) 1 to low (the ready state). By this means, when the PCI device 102 enters the state to receive data, *TRDY (Target Ready) 1 for the PCI bridge circuit 104 is set to low (the ready state).
The PCI bridge circuit 104 confirms that both the ready signals *IRDY1 and *TRDY1 are low, and then outputs the transfer data in the FIFO buffer 114 to the secondary-side PCI bus 300. At the PCI device 102, this transfer data is received in sequence.
In this way, data transfer is performed between the PCI devices 100 and 102 via the PCI bridge circuit 104.
In the above explanation of the prior art, when the data transfer rates of the primary-side bus 200 and the secondary-side bus 300 are the same, after establishing data transfer states for the buses 200, 300 on both sides, the amounts of data entering and leaving the FIFO buffer 114 are the same, so that the amount of data in the FIFO buffer 114 is maintained at a constant state.
However, as shown in FIG. 7, after data transfer from the primary-side bus 200 is initiated, there is a waiting period for finalization of the data transfer state before initiation of data transfer on the secondary-side bus 300, and the FIFO buffer 114 must be of sufficient size to accumulate the data received by the PCI bridge circuit 104 during this period.
This time waiting period for finalization of the data transfer state is, in the example of FIG. 6 and FIG. 7, determined by two lengths of time: the internal processing time for the target control circuit 110 to receive the write request from the PCI device 100 and to transmit this to the master control circuit 112, and for the master control circuit 112 to perform command generation processing for the PCI device 102 conforming to the PCI bus protocol, and the ownership capture processing-time for performing capture control of ownership of the secondary-side PCI bus 300, actually capturing ownership, and connecting to the PCI device 102. Further, when a plurality of PCI devices are connected to the PCI bus 300, this ownership capture processing time is affected by the amount of traffic on the PCI bus 300.
Consequently the size (capacity) of the FIFO buffer 114 of the PCI bridge circuit 104 must be made large, leading to an increase in the size of the chip of the PCI bridge circuit 104, and resulting in the problem that reduction of the chip size is difficult; and there is the further problem that the cost of the PCI bridge circuit 104 is increased.